The pre-fetch memory data transfer system of this sort is generally meritorious in improving the operating frequency in a clock synchronized semiconductor storage device. In actuality, in a DDR (Double Data Rate)-1 SDRAM (Synchronous Dynamic Random Access Memory), and in a DDR-2 SDRAM, the data transfer rate is improved by increasing the number of pre-fetch to 2N and to 4N (N=1; number of I/Os per address), respectively. However, the access time speedup of the chip itself cannot be achieved with ease.
Hence, only the data transmitting rate is improved, without improving the access time, by increasing the latency with increase in the operating frequency.
In actuality, while the data transfer rate of the DDR-1 SDRAM is 266 Mbps (megabits/second), the data transfer rate twice this rate, that is, 533 Mbps, may be achieved with the DDR-2 SDRAM, using the device of the similar performance.
However, with the DDR-1 SDRAM, the latency is two clocks, which is 15 ns in terms of the access time, while it is 4 clocks with the DDR-2 SDRAM, with the access time being 15 ns which is equal to that of the DDR-1 SDRAM.
With the DDR-2 SDRAM, the data path circuit is complicated by increasing the latency from 2 clocks to 4 clocks. In addition, the problem of delayed access time is presented as a result of increase in the number of stages of the output register FIFO (first-in first-out).
Moreover, there has recently been raised a demand not only for improving the data transfer rate but also for improving access time (latency).
As for a data transmitting circuit for performing 2N pre-fetch operation in the SDRAM readout circuit, reference is had to e.g. the following Patent Publication 1. This Patent Publication 1 discloses the configuration in which, for decreasing the peak current at the time when 32-bit data read out to a main input/output line (MIO line) are sensed by a main amplifier circuit and transmitted in parallel through the global input/output line (GIO line) to an output register, first output data are output with a timing shift relative to second output data.
[Patent Document 1]
JP Patent Kokai Publication No.JP-P2002-25265A (pages 7 and 9 and FIGS. 4 and 9)
FIG. 11 shows a typical example of a 2N pre-fetch data transfer circuit at the time of reading a conventional DDR-1 SDRAM. FIG. 12 is a timing diagram showing an example of the readout operation of the configuration shown in FIG. 11. As may be apparent from comparison with FIG. 1 (configuration of the embodiment of the present invention), as later explained, the configuration of FIG. 11 is such that data for one clock cycle is not held on the GIO line. With the design specifications of the SDRAM, a read command (READ) can be entered for the rise of each of the external clock signal CK, as shown in FIG. 12. If data is held on the GIO line for one clock period, a given read data collides against the next read data on the GIO line to give rise to malfunctions. Hence, data transfer occurs using a signal generated with one-shot pulses (MAB0 and MOE0) as from the clock cycle during which the read command has been entered (such as CK [0] of FIG. 12), such that it is necessary to transfer the data during one clock cycle period until the next clock cycle (such as CK[1] of FIG.12).
Referring to FIGS. 11 and 12, an MA control circuit 110A, supplied with a read clock RCLK0, generated from the external clock signal CK, to output the main amplifier output control signals MAE0 and MOE0, generates one-shot pulses (output control signals MAE0 and MOE0), based on the rising edge of the read clock RCKL0 and on the rising edge of a signal corresponding to a delayed version of the read clock RCKL0. In FIG. 11, the selection circuit 102 interchanges the connection across two inputs and two outputs so that, out of read data of even addresses and odd addresses, the data to be output first and data to be output later will be output to the F-GIO line and to the S-GIO line, respectively, in accordance with the start address. The latch circuit 103 delays data to be output later, in accordance with the start address, out of the read data of even and odd addresses, to output the so delayed data to the S-GIO line. The selection circuit 108A selects two outputs of the output register (FIFO, based on the rising edges and the falling edges of the clock signal CK20) (having the same frequency as that of the external clock signal) to output the selected outputs as serial data. An output of the last stage of the four-stage latch circuit 106, issued by the rise of the clock signal CK, is selected by the rise of the clock signal CK20, while the output of the last stage of the four-stage latch circuit 107, issued by the rise of the clock signal CK20, is selected by the fall of the clock signal CK20. An output buffer 109 receives an output from the selection circuit 108A to send the output to an external data terminal DQ.